Circuit with multiple output voltages for multiple analog to digital converters

ABSTRACT

A circuit for generating at least two output voltages in response to an input current. A first stage comprises a first impedance for providing a first output voltage when the input current passes through the first impedance. At least a second stage comprises a second impedance coupled to the first impedance, wherein the second impedance provides a second stage voltage when the input current passes through the second impedance. At least a second output voltage is equal to the sum of the second stage voltage and the first output voltage. The second stage further comprises a second stage shunt operable to shunt the input current away from the second impedance when the magnitude of the second output voltage is above a predetermined amount.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to circuits for use with analog-to-digitalconverters (ADCS) and, in particular, to circuits that providemultirange output voltages for multiple ADCs.

2. Description of the Related Art

ADCs are used to convert an analog voltage to a digital signal. In someapplications, the analog voltage has a magnitude which is proportionalto the magnitude of an input signal to be monitored. For example, theinput signal may be an input current flowing in a given current path.This input current may drive a primary winding of a current transformer,which produces a current in the secondary winding of the transformer,which is proportional to the input current. The secondary windingcurrent may be applied to a known impedance, such as a resistance, toprovide an analog voltage, which has a magnitude proportional to themagnitude of the secondary winding current and, thus, to the magnitudeof the input current. The windings of the transformer and value of theresistance may be selected so that the range of the analog voltage forthe expected range of the input current will be within the analogvoltage input range of an ADC, which in turn converts the analog voltageto a digital signal, which can then be used to monitor the magnitude ofthe input current.

One problem with such conventional circuits utilizing ADCs is that theinput signal to be monitored may have wide magnitude variations, whichrequires an ADC having a large dynamic range in order to accuratelymeasure the signal's magnitude at both low and high levels.Unfortunately, ADCs capable of measuring a large dynamic range, forexample larger than 10 bits, can be relatively expensive and thusunattractive.

Another problem exists in some configurations in which the secondarywinding current is forced through a relatively large resistance, whichcauses a relatively large voltage signal to be produced when thesecondary winding current is passed through the resistance. This imposesa large burden on the transformer, which could result in saturation,causing distortion and thus reducing the efficiency and performance ofthe transformer. Such large voltage signals can also cause damage to theADC.

SUMMARY OF THE INVENTION

A circuit for generating at least two output voltages in response to aninput current. A first stage comprises a first impedance for providing afirst output voltage when the input current passes through the firstimpedance. At least a second stage comprises a second impedance coupledto the first impedance, wherein the second impedance provides a secondstage voltage when the input current passes through the secondimpedance. At least a second output voltage is equal to the sum of thesecond stage voltage and the first output voltage. The second stagefurther comprises a second stage shunt operable to shunt the inputcurrent away from the second impedance when the magnitude of the secondoutput voltage is above a predetermined amount.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a circuit in accordance with thepresent invention; and

FIG. 2 depicts the output voltages of the circuit of FIG. 1 versus aninput current.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to FIG. 1, there is shown a schematic diagram of a circuit100 in accordance with the present invention. Circuit 100 includes acurrent transformer 102 having primary winding or coil L₁ and secondarywinding or coil L₂, which have a certain turn ratio to one another.Transformer 102 further includes core 105. Each terminal of secondarywinding L₂ is coupled to node 110 through a respective diode of bridgerectifier 150.

Circuit 100 further comprises stages 121, 122, and 123. Stage 121comprises resistor R₁, coupled between nodes 110 and 111. Stage 122comprises resistor R₂, coupled at one terminal to node 112, and at itsother terminal to node 111, to a terminal of resistor R₁, to a terminalof resistor R₆, and to the emitter of transistor Q₁. Resistor R₆ iscoupled at its other terminal to the base of transistor Q₁, to aterminal of resistor R₈, and to the emitter of transistor Q₃. ResistorR₈ is coupled at its other terminal to the base of transistor Q₃ and tothe anode of zener diode Z₁. The collector of transistor Q₃ is coupledto a terminal of resistor R₁₀. The other terminal of R₁₀ is coupled tothe cathode of zener diode Z₁ and to a terminal of resistor R₄. ResistorR₄ is coupled to the collector of Q₁, to node 112, and to resistor R₂through resistor R₇.

Stage 123 comprises resistor R₃, coupled at one terminal to node 113,and at its other terminal to node 112, to a terminal of resistor R₂, toa terminal of resistor R₇, and to the emitter of transistor Q₂. ResistorR₇ is coupled at its other terminal to the base of transistor Q₂, and toa terminal of resistor R₄. Resistors R₄ and R₇ are thus components ofboth stages 122 and 123. Resistor R₄ is coupled at its other terminal tothe cathode of zener diode Z₁, to resistor R₁₀, to resistor R₉, and tothe emitter of transistor Q₄. Resistor R₉ is coupled at its otherterminal to the base of transistor Q₄ and to the anode of zener diodeZ₂. The collector of transistor Q₄ is coupled to a terminal of resistorR₁₁. The other terminal of resistor R₁₁ and the cathode of zener diodeZ₂ are coupled to resistor R₅ and to each terminal of secondary windingL₂ through a is respective diode of bridge rectifier 150. The otherterminal of resistor R₅ is coupled to the collector of transistor Q₂, toresistor R₃, and to node 113.

In one embodiment, the resistors of circuit 100 have the followingvalues: R₁ =12.5 Ω; R₂ =187.5 Ω; R₃ =3 KΩ; R₄ =866 Ω; R₅ =13.7 KΩ; R₆=10 KΩ; R₇ =10 KΩ; R₈ =10 KΩ; R₉ =10 KΩ; R₁₀ =82 Ω; R₁₁ =82 Ω. Zenerdiodes Z₁ and Z₂ each have reverse breakdown voltages of 15 V.

First current I₁, driven by current source 101, flows through primarywinding L₁ of transformer 102. A proportional alternating current I₃ isthereby generated at secondary winding L₂. Alternating current I₃ isrectified by bridge rectifier 150 to generate rectified second currentI₂, which is applied to stage 123 at the junction of resistors R₁₁, R₅,and zener diode Z₂. Secondary winding L₂ combined with bridge rectifier150 is thus a current source that generates second current I₂. Circuit100 outputs three voltages, V₁, V₂, and V₃, at nodes 111, 112, and 113,respectively, each of which is measured with respect to ground or commonnode 110. Voltages V₁, V₂, and V₃ are analog voltage signals that areapplied to ADCs 1, 2, and 3, respectively. Each ADC, in one embodiment,is a 10-bit ADC. Thus, the magnitude of each of voltages V₁, V₂, and V₃is converted to a 10-bit digital number by its respective ADC at eachsampling interval. Each of voltages V₁, V₂, and V₃ thus has a dynamicrange of 10 bits. Circuit 100 is configured to provide an 18-bit dynamicrange for the measurement of current I₂ (and thus of current I₁). Aswill be appreciated, since circuit 100 may be utilized to monitor themagnitude of second current I₂ and thus of first current I₁, either ofcurrents I₁ or I₂ may be considered as the input current converted tocorresponding voltages V₁, V₂, and V₃ and thus monitored by ADCs 1, 2,and 3. For purposes of the present description, rectified current I₂ isconsidered to be the input current, generated by the current sourceconsisting of secondary winding L₂ and rectifier 150, the magnitude ofwhich is to be monitored by ADCs 1, 2, and 3.

To provide an 18-bit dynamic range utilizing three 10-bit ADCs, themagnitudes of voltages V₁, V₂, and V₃ are selected such that V₃ is 4bits, or 16 times (2⁴ =16), larger than V₂, and V₂ is 16 times largerthan V₁. For lower magnitudes of current I₂, current I₂ flows througheach of resistors R₃, R₂, and R₁. The values of these resistors areselected so that voltages V₁, V₂, and V₃, at nodes 111, 112, and 113,are progressively larger by factors of 16. Thus, to ensure that V₂ =16 AV₁, the values of the resistors are selected such that R₂ +R₁ =16 A R₁.Similarly, to ensure that V₃ =16 A V₂, the values of the resistors areselected such that R₃ +R₂ +R₁ =16 A (R₂ +R₁). Thus, stages 121, 122, 123each provide a resistance for current I₂ to be multiplied by to providethe appropriate output voltage for that stage. For example, stage 123provides resistor R₃. When current I₂ flows through resistor R₃, thenthe incremental voltage produced thereacross, when added to voltage V₂with which it is in series, provides voltage V₃, having a magnitude 16times larger than that of V₂.

Referring now to FIG. 2, there is depicted the output voltages V₁, V₂,and V₃ of circuit 100 of FIG. 1 versus current I₂. In one embodiment,each of ADCs 1, 2, and 3 is configured to operate within a range of 50mV to 1.25 V, the maximum reading of each ADC. At low currents ofapproximately 100 μA, V₁ ≈1.25 mV, V₂ ≈20 mV, and V₃ ≈320 mV. Thus, atthis current magnitude, the most sensitive reading can be provided byADC 3 measuring V₃. At a higher current I₂ magnitude, such as 1 mA, V₃is larger than 1.25 V and is thus too large for ADC 3 to provide anaccurate measurement. Thus, at this higher current, the reading of themagnitude of V₂ provided by ADC 2 may be utilized. At higher currents,such as 10 mA, ADC 1, which measures V₁, may be utilized.

ADCs 1, 2, and 3 may be utilized in this fashion to provide an effective18-bit resolution measurement of the magnitude of currents I₂ and I₁.When input current magnitude is lower, greater resolution may beprovided by using the lower 10-bits of the 18-bit resolution provided byADC 3. When input current magnitude is highest, the upper 10-bits of the18-bit overall resolution may be obtained from ADC 1. As will beappreciated by those skilled in the art, ADCs 1, 2, and 3 may beutilized in this fashion by always selecting the reading from the ADChaving the largest-magnitude input voltage that is also not greater thanthe maximum allowable input voltage for ADCs. For example, a programrunning on a processor may constantly monitor the reading of V₁ providedby ADC 1. Whenever V₁ is greater than approximately 78 mV (the point atwhich V₂ =1.25 V), ADC 1 will be utilized to measure the input current.Whenever V₁ is greater than approximately 5 mV (the point at which V₃=1.25 V) but less than approximately 78 mV, ADC 2 will be utilized tomeasure the input current. Whenever V₁ is less than approximately 5 mV,ADC 3 is utilized to measure the input current.

If stages 122 and 123 consisted exclusively of resistors R₂ and R₃,then, at higher input currents, for example when ADC 1 is utilized tomeasure V₁, voltages V₂ and V₃ would be 16 and 256 times larger,respectively, than V₁. Such large voltages could damage ADCs 2 and 3,and also place an undesirable burden on transformer 102, as explainedpreviously. Therefore, in the present invention, stages 122 and 123provide shunting means 132 and 133 which shunt most of current I₂ awayfrom the stages' respective resistors R₂ and R₃. In stage 122, shuntingmeans 132 consists of the components of stage 122 other than resistorR₂. In stage 123, shunting means 133 consists of the components of stage123 other than resistor R₃. As illustrated in FIG. 2, at an inputcurrent I₂ of approximately 1 mA, voltage V₃ is approximately 3 V, and,as input current I₂ increases, voltage V₃ starts to "fold back" to avoltage having a slightly larger magnitude than that of V₂ by the timeinput current I₂ is approximately 1.3 mA, since most of current I₂ isshunted by shunting means 133 so that it no longer passes through R₃.Similarly, at an input current I₂ of approximately 15 mA, voltage V₂ isapproximately 3 V, and, as input current I₂ increases, voltage V₂ startsto fold back to a voltage having a slightly larger magnitude than thatof V₁ by the time input current I₂ is approximately 20 mA, since most ofcurrent I₂ is shunted by shunting means 132 so that it no longer passesthrough R₂.

Shunting means 133 and 132 operate as follows, as will be appreciated bythose skilled in the art. At current I₂ magnitudes below 1 mA, bothshunting means are "off," and thus allow I₂ to pass through resistors R₃and R₂. When shunting means 133 and 132 are off, their constituent zenerdiodes and transistors are off, and the shunting means appear as opencircuits to current I₂. As current I₂ reaches and begins to exceed 1 mA,the voltage drop across resistor R₅ becomes high enough such that thevoltage at the terminal of resistor R₅ coupled to the cathode of zenerdiode Z₂ turns on Z₂, causing current l_(Z2) to flow therethrough.Current I_(Z2) flows through resistor R₉, causing a voltage dropthereacross which turns on transistor Q₄.

Current thus flows through transistor Q₄ and thence through R₄ and R₇.The voltage drop across R₇ is sufficient to turn on transistor Q₂, whichthus shunts away from R₃ most of current I₂, causing the voltage V₃ to"fold back" as illustrated in FIG. 2. At this point, V₃ is slightlylarger than V₂.

Most of current I₂ thus flows through Q₂ instead of through R₃ forcurrent magnitudes above approximately 1.3 mA. At this point none of thecurrent from Q₄ flows down into shunting means 132, since Q₃ and Z₁ ofshunting means 132 are off because the voltage across R₂ is insufficientto allow current to flow through zener diode Z₁. Transistor Q₁ thusremains turned off, and current I₂ flows through stage 123 and thencethrough resistors R₂ and R₁, to develop voltages V₂ and V₁, as before.As current I₂ reaches and begins to exceed 15 mA, the voltage dropacross resistor R₄ becomes high enough such that the voltage at theterminal of resistor R₄ coupled to the cathode of zener diode Z₁ turnson Z₁, causing current I_(zl) to flow therethrough. Current I_(Z1) flowsthrough resistor R₈, causing a voltage drop thereacross which turns ontransistor Q₃. Current thus flows through transistor Q₃ and thencethrough R₆. The voltage drop across R₆ is sufficient to turn ontransistor Q₃, which thus shunts away from R₂ most of current I₂,causing the voltage V₂ to "fold back" as illustrated in FIG. 2. At thispoint, V₂ is slightly larger than V₁.

Resistors R₄ and R₅, along with zener diodes Z₁ and Z₂, are theprincipal components of circuit 100 that set the fold back points, ormaximum voltages, for ADCs 2 and 3, respectively. Resistors R₁₀ and R₁₁are used to reduce the power loss in transistors Q₃ and Q₄ at highercurrent levels.

Thus, circuit 100 is a circuit for generating output voltages V₁, V₂,and V₃ in response to an input current I₂. In one embodiment, circuit100 comprises a first stage 121 comprising a first impedance R₁ forproviding a first output voltage V₁ when the input current I₂ passesthrough the first impedance R₁, and a second stage 122. Second stage 122comprises a second impedance R₂ and a second stage shunt means 132,wherein the second impedance R₂ provides a second stage voltage V_(R2)=(V₂ -V₁) when the input current I₂ passes through the second impedanceR₂ and the second stage shunt means 132 is for shunting the inputcurrent I₂ away from the second impedance R₂ when the input current I₂is above a predetermined amount (in the example given above, 15 mA). Thesecond impedance R₂ is coupled to the first impedance R₁ so that thesecond stage voltage V_(R2), when added to the first output voltage V₁,provides a second output voltage V₂. The second stage shunt means 132preferably comprises a transistor

Q₁ for shunting the input current I₂ away from the second impedance R₂.The second output voltage V₂ is preferably a predetermined multiple(e.g., 16) of the first output voltage V₁.

In further embodiments, additional stages may be added, such as thirdstage 123. Third stage 123 comprises a third impedance R₃ and a thirdstage shunt means 133, wherein the third impedance R₃ provides a thirdstage voltage V_(R3) when the input current I₂ passes through the thirdimpedance R₃ and the third stage shunt means 133 is for shunting theinput current away from the third impedance when the input current isabove a second predetermined amount (e.g., 1 mA), wherein the thirdimpedance is coupled to the second impedance so that the third stagevoltage V_(R3), when added to the second output voltage V₂, provides athird output voltage V₃. Thus, circuit 100 of the present inventionprovides for reduced power requirements and a reduced burden on thetransformer. Central processing units (CPUs) having multiple 10-bit ADCsare also relatively inexpensive, so that the current invention providesfor a larger dynamic ADC range than is possible with a single ADC, at alower cost.

Those skilled in the art will appreciate that alternative embodiments ofthe present invention may utilized a number of stages other than three.For example, a four-stage circuit may be utilized with four ADCs andfour output voltages, in which three of the four stages provide aresistor and a shunting means. Additionally, in alternative embodiments,ADCs having a resolution other than 10-bits may be utilized. ADCs mayalso be combined with overlaps other than 4 bits, to provide aneffective resolution other than 18 bits. For example, three 10-bitresolution ADCs may be utilized, with voltages V₁, V₂, and V₃ separatedby a factor of 32 (5 bits) rather than 16 (4 bits), for an overallresolution of 20 bits instead of 18 bits.

Alternatively, three 12-bit resolution ADCs may be utilized, withvoltages V₁, V₂, and V₃ separated by a factor of 16, for an overallresolution of 20 bits instead of 18 bits.

It will be understood that various changes in the details, materials,and arrangements of the parts which have been described and illustratedabove in order to explain the nature of this invention may be made bythose skilled in the art without departing from the principle and scopeof the invention as recited in the following claims.

What is claimed is:
 1. A circuit for generating at least two variableoutput voltages in response to a variable input current, the circuitcomprising:(a) a first stage comprising a first impedance for receivingthe variable input current from a variable current source and forproviding a first output voltage when the variable input current passesthrough the first impedance; and (b) at least a second stage comprisinga second impedance coupled to the first impedance, wherein the secondimpedance provides a second stage voltage when the variable inputcurrent passes through the second impedance, further wherein at least asecond output voltage is equal to the sum of the second stage voltageand the first output voltage, the second stage further comprising asecond stage shunt operable to automatically shunt the variable inputcurrent away from the second impedance while still applying the variableinput current to the first impedance, when the magnitude of the secondoutput voltage is above a predetermined amount.
 2. The circuit of claim1, wherein the second output voltage is a predetermined multiple of thefirst output voltage.
 3. The circuit of claim 1, further comprising:(c)a third stage comprising a third impedance coupled to the secondimpedance, wherein the third impedance provides a third stage voltagewhen the input current passes through the third impedance, furtherwherein a third output voltage is equal to the sum of the third stagevoltage and the second output voltage, the third stage furthercomprising a third stage shunt operable to shunt the input current awayfrom the third impedance when the magnitude of the third output voltageis above a second predetermined amount.
 4. The circuit of claim 1,wherein the second stage shunt comprises a transistor for shunting theinput current away from the second impedance.
 5. The circuit of claim 4,wherein:the first impedance is a first resistor and the second impedanceis a second resistor; the second stage shunt further comprises a meansfor turning on the transistor when the input current is above thepredetermined amount; the transistor has base, collector, and emitterterminals; and the emitter terminal of the transistor is coupled to thejunction of the first and second resistors, the collector terminal iscoupled to the other terminal of the second resistor, and the base ofthe transistor is coupled to the means for turning on the transistor. 6.The circuit of claim 5, wherein the means for turning on the transistorcomprises third, fourth, and fifth resistors, a second transistor havingbase, collector, and emitter terminals, and a zener diode having anodeand cathode terminals, wherein the third resistor is coupled between thebase and emitter terminals of the transistor, the base terminal of thetransistor is coupled to the emitter of the second transistor andthrough the fourth resistor to the base of the second transistor and theanode of the zener diode, and the collector of the transistor is coupledthrough the fifth resistor to the collector of the second transistor andthe cathode of the zener diode.